1. Field of the Invention
The present invention relates to field-programmable-gate-array (FPGA) integrated circuit technology. More particularly, the present invention relates to on-chip circuits for testing an FPGA for the presence of defects.
2. Prior Art
Traditionally, integrated circuits are only tested for functional defects (those that become apparent no matter how slowly the chip is operated). However as semiconductor technology scales, it becomes necessary to check for other defects as well.
Methods for testing for delay defects in nonprogrammable integrated circuits, such as standard cell ASICs, are known in the prior art. Some of these are applicable also to programmable integrated circuits, including FPGAs. Other testing methods are specific to programmable integrated circuits.
There are three general categories of known test methods: at-speed functional test with the intended design; scan chain testing; and methods specific to programmable logic devices. Each is considered in turn.
In at-speed functional testing, the circuit is tested by running it as in normal operation, but using the highest specified clock frequency. This can be very effective for non-programmable integrated circuits (or for programmable integrated circuits that are already programmed with the intended design and will not be reprogrammed). However for programmable integrated circuits, the need to use the highest specified clock frequency is problematic, since this frequency is very design-dependent and end-user designs are not known at the time of testing.
Scan chains are a widely used technique for performing functional testing of non-programmable integrated circuits (e.g. standard cell ASICs). The various flip-flops in an integrated circuit are connected together to form a shift register (scan chain) independent of the normal functional logic. By putting the flip-flops in a special scan mode, test data can be shifted into and/or out of the flip-flops.
Scan chains can also be used to test for delay defects. There are two methods for using scan chains to perform delay-defect testing, launch from shift and launch from capture. One example is found in R. Madge, B. R. Benware and W. R Daasch, “Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs, IEEE Design & Test of Computers,” September-October 2003, pp. 46-53.
Common to both methods is that two clock pulses are applied at high speed and path delays exceeding the intervening time are detected. First, a test pattern is loaded using the scan chain. Signals are then launched through the delay paths either by a last pulse of the clock in scan mode (“launch from shift”), or by pulsing the clock in normal mode (“launch from capture”). After a suitable delay, the outputs of the delay paths are captured in the flip-flops by another pulse of the clock, in normal mode. In some cases it may be desirable to pulse the clock multiple times in normal mode before reading out the data.
An FPGA programmed with a particular design can also be tested for delay defects using launch and capture pulses if some means (analogous to a scan chain) is provided to control and observe the flip-flops. In an FPGA, alternatives for controlling and observing the flip-flops include a hard (built-in) scan chain, a soft (programmed as part of the design) scan chain, and a read/write probe circuit using row/column addressing. In the following discussion, the term “scan chain” will be considered to include any of these or other similar means for controlling and observing the flip-flops.
Some one-time programmable FPGAs Manufactured by Microsemi Corporation, formerly Actel Corporation, provide a probe circuit that provides random access to the flip-flops in the programmable fabric. The output of a probe circuit is made available on an external pin of the chip, providing real-time observation of a selected flip-flop output or other test point. The probe is intended to facilitate testing of the FPGA by its manufacturer and debugging of his design by the user. However this circuit is read-only, providing only observability, not controllability.
Non-programmable logic chips typically add scan chain circuitry to their flip-flops. Scan chains are a widely used technique for testing of such chips (e.g. standard cell ASICs). The various flip-flops in a chip are connected together to form a shift register (scan chain) independent of the normal functional logic. By putting the flip-flops in a special scan mode, test data can be shifted into and/or out of the flip-flops. By providing both observability and controllability, the scan chain allows fault coverage up to about 97%. This is much more than is possible if the only access was via the external pins of the chip, which justifies the additional area required to add scan chains.
In reprogrammable logic, such as SRAM- or flash-based FPGAs, testing is typically done by programming multiple test designs into the chip and applying test vectors to each design through the external pins. Because each design is specifically chosen for testing, it is not necessary to provide extra circuitry like scan chains to achieve good coverage. In fact coverage nearing 100% can be achieved. For this reason, scan chains have not previously been added to flip-flops in the programmable fabric of FPGAs.
For volume production it may sometimes be desirable to test FPGAs for use with a specific customer design. In this case, defects in circuitry not used by the particular design can be ignored. Even in this case however the testing is still generally performed by programming multiple test designs into the chip.
Flash-based FPGAs take significantly longer to program than SRAM-based FPGAs, and so can benefit from improved testing methods for volume production. It would be advantageous to be able to pre-program the FPGA only once with the specific customer design, and test it without need for further reprogramming (e.g. of multiple test designs). Some means of controlling and observing flip-flops is required. One possibility is to add explicit scan chains to the user's design and implement them in the programmable fabric (soft gates). However this consumes expensive logic capacity. Some equivalent of scan chain but better suited to FPGAs is required.
Some FPGAs are designed for low power applications. Here it is desirable to be able to save the system state information (e.g. data in flip-flops and RAM blocks) to non-volatile bulk storage before powering down the FPGA. Then when the FPGA is powered up again, the state can be restored from the non-volatile memory. The Lattice Semiconductor XP2 FPGAs provide this capability for RAM blocks, but not for flip-flops. Saving and restoring the flip-flop state also requires some means for observing and controlling the flip-flops.